1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device of a MOS structure, and more particularly to a method for fabricating a charge coupled device.
2. Description of the Related Art
A method for fabricating a typical conventional Charge Coupled Device (CCD) is first explained to assist the understanding of the invention. FIGS. 1A-1E are cross-sectional views in the direction of charge transfer of such a conventional charge coupled device. As seen therefrom, after an N type CCD channel 2 and a P.sup.+ type channel stopper (not shown) are formed, a first gate oxide film 4 is formed using a thermal oxidation process (FIG. 1A). Next, a first layer polycrystalline silicon film 6 is deposited by a Chemical Vapor Deposition (CVD) process, an impurity is doped, a pattern 7 of photoresist (PR) is formed, and a first layer transfer electrode 8 is formed by etching the silicon film 6 using a plasma etching process (FIGS. 1B and 1C). Then, by etching the entire oxide film, at least the first gate oxide film 4 at regions where second layer transfer electrodes are to be formed is removed, and then a second gate oxide film 11 is formed by carrying out a thermal oxidation process again (FIG. 1D). The second layer transfer electrode 13 is formed from the second layer polycrystalline silicon film using the same procedure as for the first layer transfer electrode (FIG. 1E).
According to the above method, the first gate oxide film 4 is required to be sufficiently thick so that, during the plasma etching of the first layer polycrystalline silicon film 6, any damaging of a silicon substrate surface (oxide film/silicon interface) of at least the regions where the second layer transfer electrodes are to be formed is prevented. Also, the oxidation condition of the second gate oxide film 11 requires that an oxide film, from which the necessary break down voltage characteristics can be obtained between the first and second polycrystalline silicon transfer electrodes 8 and 13, be formed on a surface of the first layer transfer electrode 8.
The problem in the above conventional method is that, if the second gate oxide film 11 is made thicker, in an attempt to enhance the insulating properties between the first and second layer transfer electrodes 8 and 13, the quantity of storable/transferable charges is decreased. If the second gate oxide film 11 is made thinner, in an attempt to increase the quantity of storable/transferable charges, the insulating properties between the first and second layer transfer electrodes 8 and 13 are deteriorated. A method intended to solve the above contradiction is proposed in Japanese Patent Application Kokai Publication Nos. Hei 2-189937 and Hei 2-292834.
The method proposed in the above Japanese Patent Application Kokai Publication No. Hei 2-189937 is explained with reference to FIGS. 2A-2H. A first gate oxide film 4 having a thickness of several hundred Angstroms is grown by a thermal oxidation process on an N type CCD channel 2 which is formed in a P type silicon substrate 1, and further a nitride film 14 having a thickness of several hundred Angstroms is deposited by a CVD process (FIG. 2A). Thereafter, by using a photolithography process, the nitride film 14 at regions where first layer transfer electrodes 8 are to be formed is etched away, and regions where second layer transfer electrodes are to be formed later are left in place (FIG. 2B). Then, a first polycrystalline silicon film 6 is deposited on the resulting structure by a CVD process (FIG. 2C). This first polycrystalline silicon film 6 is selectively etched using a photolithography process thereby forming a first layer transfer electrode 8 (FIG. 2D). An insulating oxide film 12 is deposited to a sufficient thickness on a surface of the first layer transfer electrode 8 by a thermal oxidation process (FIG. 2E). At this time, because of resistance to oxidation of the nitride film 14, there is almost no growth of an insulating oxide film on the nitride film 14. Thereafter, the nitride film 14 is selectively etched away, followed by the oxide film etching (FIG. 2F). In this case, the insulating oxide film 12 is sufficiently thick so that, after the silicon substrate at the regions where the second layer transfer electrodes 13 are to be formed is exposed by the etching away of the first gate oxide film 4, the insulating oxide film 12 on the surface of the first layer transfer electrode 8 has a thickness sufficient to obtain the necessary break down voltage between the first layer and second layer polycrystalline silicon transfer electrodes. Thereafter, a second gate oxide film 11 having a thickness of several hundred Angstroms is grown on the entire surface by a thermal oxidation process (FIG. 2G). Then, a second layer polycrystalline silicon film is grown on the entire surface of the resulting structure, and a second layer transfer electrode 13 is formed by selectively etching the second layer polycrystalline silicon film (FIG. 2H).
In the publication proposing the above method, it is explained that, since the first oxide film, the insulating oxide film and the second gate oxide film are formed independently from one another, the insulating oxide film can be made thick while each of the gate oxide films is made thin.
The method proposed in the Japanese Patent Application Kokai Publication No. Hei 2-292834 is explained with reference to FIGS. 3A-3F. A first gate oxide film 4 having a thickness of several hundred Angstroms is grown by a thermal oxidation process on an N type CCD channel 2 which is formed in a P type silicon substrate 1 (FIG. 3A). Then, after a first layer polycrystalline silicon film 6 is deposited by a CVD process and an impurity is diffused, an insulating oxide film 12 is formed on a first layer polycrystalline silicon film 6 by a thermal oxidation process (FIG. 3B). Thereafter, by selectively etching away the insulating oxide film 12, the first layer polycrystalline silicon film 6 and the first gate oxide film 4, the first layer transfer electrodes 8 are formed, and a silicon substrate surface at regions where second transfer electrodes 13 are to be formed is exposed (FIG. 3C). Then, an oxide film having a thickness of several hundred Angstroms is deposited by a CVD process, and the resulting structure is anisotropically etched until the substrate is exposed and a sidewall oxide film 15 is formed (FIG. 3D). Then, a second gate oxide film 11 having a thickness of several hundred Angstroms is formed by a thermal oxidation process (FIG. 3E). Further, a second layer polycrystalline silicon film is deposited by a CVD process on the entire surface, and this film is patterned to form a second layer transfer electrodes 13 (FIG. 3F).
In the publication proposing the above method, it is explained that, since the insulating oxide film and the sidewall oxide film that cover the first layer transfer electrode, and the second gate oxide film are formed independently from one another, the thickness of each of such films can be appropriately selected.
In the conventional method explained with reference to FIGS. 1A-1E, there are above explained requirements as to the thicknesses of the first gate oxide and second oxide films, and this in turn places limitations as to the charge transfer performance of the charge coupled device.
The above Japanese Patent Application Kokai Publication Nos. Hei 2-189937 and Hei 2-292834 are intended to propose solutions to the problems explained above, but there are also problems in their proposals.
According to the proposal made in the Japanese Patent Application Kokai Publication No. Hei 2-189937, which is shown in FIGS. 2A-2H, a nitride film is formed on a first gate oxide film, and this nitride film is selectively etched away with a region where a second layer transfer electrode is to be formed being covered. Thus, it is arranged such that, when an insulating oxide film is grown on a surface of a first layer transfer electrode (FIG. 2E), there is no formation of a thick oxide film at the region where the second layer transfer electrode is to be formed. The nitride film is normally patterned by plasma etching so that the first gate oxide film 4 is required to have a thickness such that, during the plasma etching of the nitride film 14, at least a silicon substrate surface (oxide film/silicon interface) of the first layer transfer electrode formation region may not suffer from etching damages. This means that the requirement as to the thickness needed during the fabrication is not completely removed. Further, the first gate oxide film 4 has already received the damage during the plasma etching of the nitride film, and the formation of the first layer transfer electrode thereon results in problems leading to the deterioration of the break down voltage properties between the first layer transfer electrode and the silicon substrate, and to increased dark currents in the charge coupled device.
According to the proposal in the Japanese Patent Application Kokai Publication No. Hei 2-292834, as shown in FIGS. 3A-3F, an insulating oxide film 12 is formed prior to the patterning of a first layer polycrystalline silicon film (FIG. 3C), and an oxide film 15 is grown by a CVD process after the patterning of a first layer transfer electrode 8. The oxide film grown 15 is anisotropically etched until a surface of a silicon substrate is exposed, thereby leaving the oxide film 15 only at the sides of the first layer transfer electrode 8 so as to form sidewalls of the oxide film. The anisotropical etching is a kind of plasma etching. Thus, this method directly causes the etching damage to occur on the silicon substrate surface at the second layer transfer electrode formation region. It is difficult to eliminate such etching damage during the subsequent thermal treatment or oxidation, and this may lead to an increase in dark currents, to a deterioration of transfer efficiency, or, in the worst case, to a complete failure of the transfer function in the charge coupled device.